FIG. 1A illustrates a conventional phase locked loop, which may include a phase frequency detector (PFD) 10, a charge pump (CP) 12, a loop filter (LF) 14, a voltage controlled oscillator (VCO) 16, one or more dividers 18-1, 18-2, and/or one or more dividers 20.
The phase frequency detector (PFD) 10 may receive an external clock signal ECLK and generate an UP or DN signal in response to a phase difference between the external clock signal ECLK and a feedback clock signal DCLK. When the phase of the external input signal ECLK leads that of the feedback clock signal DCLK, the UP signal is activated. When the phase of ECLK lags that of DCLK, the DN signal is activated.
The charge pump (CP) 12 and/or the loop filter (LF) 14 may increase the level of a control voltage (Vc), in response to the activated UP signal and may decrease the level of the control voltage Vc, in response to the activated DN signal.
For example, when the frequency of ECLK is 1 GHz, in order to acquire one or more final internal clocks of 2 GHz frequency, a conventional voltage controlled oscillator (VCO) 16 may generate two clock signals CLK and CLKB, each with a frequency of 4 GHz. The divider 18-1 may divide the clock signal CLK to generate two clock signals ICLK0, ICLK180, each with a frequency of 2 GHz. The divider 18-2 may divide the inverted clock signal CLKB to generate two clock signals ICLK90, ICLK270, each with a frequency of 2 GHz.
The divider 20 may receive one of the clock signals ICLK0, ICLK180, ICLK90 and ICLK270 and output the divided clock signal DCLK, with a frequency of 1 GHz, which equals the frequency of ECLK.
That is, in order to acquire final internal clock signals ICLK0, ICLK180, ICLK90 and ICLK270 having a higher frequency than that of ECLK, the divider 20 is necessary. In other words, when a PLL does not include the divider 20, the frequencies of the final internal clocks ICLK0˜ICLK270 are equal to the frequency of external input clock ECLK. However, the frequency of each of CLK and CLKB must be four times higher than that of ECLK to generate final internal clocks ICLK0˜ICLK270, with a frequency twice that of ECLK.
As a result, a problem with conventional phase locked loops is that higher frequency internal clock signals (for example, 4 GHz or higher) may be difficult to generate from a VCO when a power voltage (VCC) is low (for example, less than 2VDD or under 1.8V). Further, conventional phase locked loops may have a larger chip area as a result of the number of dividers.
FIG. 1B illustrates another conventional phase locked loop. The conventional phase locked loop of FIG. 1B includes some of the same elements as that of FIG. 1A. In addition to one or more dividers 18-1, 18-2, and one or more dividers 20, the conventional phase locked loop of FIG. 1B may further include one or more dividers 18-3, 184, 18-5, and 18-6. As shown, the frequency of each of CLK and CLKB is eight times higher than that of ECLK while the frequency of each of iCLK0˜iCLK270 is four times higher than that of ECLK. Further, the frequency of each of ICLK0˜ICLK315 is two times higher than that of ECLK.
As an example, if the frequency of ECLK is 1 GHz, the frequency of CLK and CLKB is 8 GHz, the frequency of iCLK0˜iCLK270 is 4 GHz, and the frequency of ICLK0˜ICLK315 is 2 GHz. Under low power supply voltage conditions (for example, less than 2VDD), a conventional VCO 16 cannot generate the output clocks CLK and CLKB with a frequency of 8 GHz.
FIG. 2 illustrates a conventional voltage controlled oscillator, for example, VCO 16 of FIGS. 1A or 1B. The conventional voltage controlled oscillator may include a first ring oscillator 16-1 including one or more inverters I1, I2, I3, formed in a loop configuration, a second ring oscillator 16-2 including one or more inverters I4, I5, I6, formed in a loop configuration (for example, the same configuration as the first ring oscillator 16-1) and a latch circuit 16-3 including one or more inverters I7, I8, for latching CLK and CLKB.
The frequency of the output clock CLK/CLKB may be controlled in response of the level of Vc. When the level of Vc is increased, the frequency of the output clock CLK/CLKB may be increased. When the level of Vc is decreased, the frequency of the output clock CLK/CLKB may be decreased. A problem may be that the Vc is at too low a level (if supplied by a low power supply) so that high frequency output clock signals CLK/CLKB (for example, 4 GHz or more) can not be generated.
FIG. 3A is a timing diagram illustrating example operation of a conventional phase locked loop, for example, the conventional phase locked loop of FIG. 1A.
The voltage controlled oscillator 16 may generate two clock signals CLK and CLKB, having a phase difference of 180°, and which have a frequency four times higher frequency than that of ECLK. The frequency of each of ICLK0˜ICLK270 may be two times higher than that of ECLK.
FIG. 3A illustrates that an internal clock ICLK0 is locked with the external clock ECLK. When a power supply voltage is a higher level, all of the above internal clock signals may be generated normally. However, when a power supply voltage is a lower level, it is impossible to generate the timing diagram of FIG. 3A.
FIG. 3B is a timing diagram illustrating example operation of a conventional phase locked loop, for example, the conventional phase locked loop of FIG. 1B.
The voltage controlled oscillator 16 may generate two clock signals CLK and CLKB having a phase difference of 180°, and which have a frequency eight times higher than that of ECLK. The frequency of each of iCLK0˜iCLK270 may be four times higher than that of ECLK. The frequency of each of ICLK0˜ICLK315 may be two times higher than that of ECLK.
FIG. 3B illustrates that an internal clock ICLK0 is locked with the external clock ECLK. When a power supply voltage is a higher level, all of the above internal clock signals may be generated normally. However, as set forth above, when a power supply voltage is a lower level, it is impossible to generate the timing diagram of FIG. 3B.